Dr. Michiko Inoue Gave a Talk on “An ECC-based memory architecture with online self-repair capabilities for reliability enhancement” at IICT, BUET on 8th March, 2016 at 5PM at the IICT Seminar Room
Embedded memory is extensively being used in SoCs, and is rapidly growing in size and density. To keep up with the development pace of nanoscale devices, enhancement methods for yield and reliability must overcome the barriers set forth by advent of new technology. To address the issue of reliability, periodic online field test and repair are implemented by using synergistic approach of employing redundancy and ECC to repair or correct both hard errors and soft errors. In this paper, an online remap strategy for memory repair, which ensures ‘fresh’ memory words are always used until the spare words run out, is proposed. The improvement of reliability for memory architectures and the area overhead introduced by the proposed scheme is evaluated.
Michiko Inoue received her B.E., M.E, and Ph.D degrees in computer science from Osaka University in 1987, 1989, and 1995 respectively. She had worked at Fujitsu Laboratories Ltd. from 1989 to 1991. Currently, she is a Professor of Graduate School of Information Science, Nara institute of Science and Technology (NAIST). Her research interests include distributed algorithms, parallel algorithms, graph theory and design and test of digital systems. She is a member of Science Council of Japan, IEEE, the Institute of Electronics, Information and Communication Engineers (IEICE), the Information Processing Society of Japan (IPSJ), and Japanese Society for Artificial Intelligence.